This invention relates to high-speed serial data communication, and more particularly to methods and apparatus for monitoring the condition of certain aspects of a high-speed serial data signal at any point in circuitry that is handling that signal. The data rate of a typical high-speed serial data signal may be in the range of about 6-10 Gbps (giga-bits per second), although lower and higher data rates are also well known.
In high-speed serial interface (“HSSI”) applications, the input signal of a receiver (“RX”) integrated circuit device (“chip”) is usually attenuated and distorted due to frequency-dependent signal loss across interconnects (e.g., printed circuit board (“PCB”) traces from a transmitter (“TX”) chip on the PCB to the RX chip on the PCB). This causes inter-symbol interference (“ISI”), which affects the margins for clock and data recovery (“CDR”) circuitry on the RX chip. Various RX equalization techniques have been employed to improve the input signal before the CDR circuitry to lower the bit error rate (“BER”) of the recovered data.
A common way to evaluate ISI is with a so-called eye diagram of the serial data signal. An eye diagram is a super-positioning of the waveform of multiple data bits in the signal on the time interval of a single bit (a so-called unit interval or UI). An eye diagram visualizes the ISI and other jitter components of the high-speed serial data signal. An oscilloscope can be used to generate an eye diagram (e.g., by connecting probes of the oscilloscope to signal pins on the chip handling the signal).
Users of RX chips that include equalization circuitry would sometimes like to have the ability to observe the eye diagram of a high-speed serial data signal after processing by the equalization circuitry on the chip. Such a feature can have several benefits. First, such an on-chip eye monitor can work like an oscilloscope to probe the internal high-speed nodes that cannot be observed by probing external pins of the chip. Second, the resulting eye diagram shows the RX equalization results, and this information can be used as a basis for making adjustments to the kind(s) and/or amount(s) of equalization being employed. Third, an on-chip eye monitor can help a system engineer analyze, diagnose, and debug HSSI devices without probes and an oscilloscope in the field.
Yasumoto Tomita et al., “A 10-Gbp/s Receiver With Series Equalizer and On-Chip ISI Monitor in 0.11-μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, April 2005, pp. 986-93, shows use of high-frequency clock signals and switched capacitors to sample and monitor ISI effects. In contrast to what this reference shows, the present invention uses low-frequency clocks to sample a repetitive data pattern and construct an eye diagram. This avoids the need for over-sampling of data signals having data rates like 6-10 Gbps, which over-sampling can be impractical or at least undesirable because of consequent power, area, and complexity considerations.